The present invention generally relates to an integrated circuit (IC) diagnosis technique and, more particularly, to an apparatus and a method for determining the location of an IDDQ defect in an integrated circuit.
Presently, there are several different types of testing methods for detecting faults in integrated circuits. However, one particular method has been widely accepted and successful in the electronics industry. This one particular method comprises a complementary metal oxide semiconductor (CMOS) integrated circuit test method which is known as quiescent power supply current, or IDDQ, testing.
IDDQ testing is attractive because it can achieve high fault coverage with relatively few test patterns, and can detect certain types of unique defects (for example, subtle transistor leakage mechanisms and highly resistive bridges) that logic and functional testing may not detect.
IDDQ testing is based on the observation that certain commonly occurring semiconductor defects, such as bridges or shorts between metal lines, will cause an IC to draw extra supply current, even when the IC is in a xe2x80x9cquiescentxe2x80x9d state in which all of its intended conduction paths are turned off. Such a defect forms an unintended conduction path between two or more electrically active regions of the IC, and extra current will result (i.e., the defect is xe2x80x9cactivatedxe2x80x9d) whenever these regions are at different electrical potentials.
Such a defect, which is detectable by an IDDQ test, will be referred to as an xe2x80x9cIDDQ defectxe2x80x9d hereafter. Also, the current resulting from a defect will be referred to as xe2x80x9cIDDQ defect currentxe2x80x9d. It should be noted that an IDDQ defect may not be in close physical proximity to the sites in the power and ground networks where the additional current enters and exits the chip. The current arising from a bridge between two signal lines, for example, has its source and sink in the two circuits which drive the bridged lines, either or both of which may be far removed from the location of the actual defect. Hereinafter, for the sake of brevity, any reference to the existence of an IDDQ defect within a particular physical area is intended to include the possibility that the area identified contains only a circuit of which output signal line contains a defect, and that the defect itself may in fact lie outside the area identified.
A single reading is typically obtained by applying a predetermined test pattern to the primary inputs of an IC, allowing the IC to xe2x80x9csettlexe2x80x9d into a quiescent state, and then measuring the current drawn by the IC in the quiescent state. An IDDQ test normally comprises the application of several such test patterns and measurements. Each pattern places the IC into a different electrical state, thereby increasing the likelihood of activating, and thus of detecting, any IDDQ defects present on the IC.
A semiconductor manufacturer""s ability to improve its manufacturing yield depends upon successful physical failure analysis (PFA), in which the root cause of an IC""s failure is determined. Central to successful PFA is the ability to determine the physical location of a defect on an IC. Because traditional IDDQ testing measures current at a single point in the IC""s power supply, each reading indicates the current drawn by the entire IC. For this reason, traditional IDDQ measurements provide no direct information about the physical location of the defects they detect. A means for determining the location of a defect directly from IDDQ measurements could improve the accuracy and effectiveness of PFA, enabling more rapid improvement of manufacturing yield.
In the absence of such a method, one existing means of locating an IDDQ defect is software diagnosis. Given a logic simulator which can determine the internal electrical state of the IC during each IDDQ measurement, and an indication of which IDDQ measurements xe2x80x9cfailedxe2x80x9d (detected the defect) and which xe2x80x9cpassedxe2x80x9d, IDDQ diagnostic software can determine likely defect sites by identifying internal circuit nodes which, if defective, could explain which patterns pass and fail.
Although test and diagnosis offer unique benefits to IC manufacturers, the effectiveness of IDDQ testing has been generally diminished because of its increasing difficulty of detecting IDDQ defect current in the presence of the overwhelmingly higher background current (e.g., substrate current). Such background current is a very typical phenomenon in modern integrated circuit devices. Even a defect-free integrated circuit draws a certain amount of background current while in a quiescent state because of a normal leakage phenomenon within individual devices (e.g., transistors) within an IC device. As the number of transistors in advanced integrated circuit devices has exponentially grown, the background current arising from their cumulative leakage has increased drastically.
Because the current resulting from an activated IDDQ defect is typically small, the xe2x80x9csignal-to-noisexe2x80x9d ratio in IDDQ testing (that is, the ratio of defect current to normal background current) has become so low that some IC manufacturers have abandoned IDDQ testing altogether as ineffective for their high-performance IC""s. A means of increasing this signal-to-noise ratio would thus not only extend the applicability of IDDQ testing for defect detection, but would improve the capability of software diagnosis by enabling xe2x80x9cpassingxe2x80x9d and xe2x80x9cfailingxe2x80x9d patterns for a given IC to be distinguished more readily.
An object of the present invention is to provide an improved and more accurate method for testing an integrated circuit by improving a ratio between defect current and background current within the integrated circuit.
Another object of the present invention is to provide a method for improving the ratio between defect current and background current for integrated circuit testing by dividing an integrated circuit into a plurality of areas and individually measuring an amount of IDDQ defect current generated in each area.
Still another object of the present invention is to provide an improved and accurate method of determining the presence of an IDDQ defect based on the measured amount of IDDQ defect current generated in each area.
Further, an object of the present invention is to provide an apparatus and a method for determining a location of an IDDQ defect within the integrated circuit based on the measured amount of IDDQ defect current generated in each area.
A further object of the present invention is to provide a method for creating an IDDQ current map of an integrated circuit based on the measured amount of IDDQ defect current generated in each area.
Additional objects and other features of the present invention will be set forth in part in the description which follows and will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The objects and advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other objects and advantages are achieved in part by a method of testing an integrated circuit which has a plurality of terminals on a surface thereof. The surface is divided into a plurality of areas, each area is provided with at least one of said plurality of terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. Amounts of the IDDQ defect current transferred to said plurality of terminals are measured. Based on the amount of said IDDQ defect current measured at the plurality of terminals, it is determined whether each area includes said IDDQ defect.
Thus, by dividing an integrated circuit into a plurality of areas and measuring the IDDQ defect current generated within each area, the present invention significantly increases the ratio between signal (IDDQ defect current) and noise (e.g., substrate leakage current). With significantly reduced noise interference, the present invention enables determining whether each area includes any IDDQ defect more accurately.
Also, the present invention enables determining the location of the IDDQ defect within the areas determined to include the IDDQ defect. First, one of said areas determined to include an IDDQ defect is selected for the IDDQ defect location determination. The selected area is divided into a plurality of subsections, each subsection is provided with a corresponding one of the terminals bounding the selected area. Based on the amounts of the IDDQ defect current measured at the terminals bounding the selected area, it is determined which subsection includes the IDDQ defect based on the amount of the IDDQ defect current measured at the terminals bounding the selected area.
Further, the present invention enables determining the location of the IDDQ defect within a selected subsection. The selected subsection is divided into a plurality of sub-subsections. It is determined which sub-subsection includes the IDDQ defect based on the ratio between (a) an amount of said IDDQ defect current forwarded to the terminal provided for the selected subsection and (b) an amount of a sum of said IDDQ defect current measured at the terminals bounding said selected area. Hence, in addition to merely detecting the presence of an IDDQ defect, the present invention enables the determination of the location of an IDDQ defect within an integrated circuit.
The application of the present invention is not limited to devices manufactured by using CMOS techniques. The present invention can be applied to any kind of IC devices which include circuitry capable of disabling DC currents, controlling power and ground supply connections or voltage levels thereof, or settling the device to be in a low current state for IDDQ measurement. Also, the present invention can be used with standard magnitude versus threshold IDDQ testing, as well as more complex schemes, such as delta IDDQ testing. One skilled in the art will be able to use this invention in many other applications.